Voltage regulators such as low dropout (LDO) voltage regulators are widely used devices in electronic systems. Such circuits are usually applied in the voltage supply chain to provide a precise and time-stable supply voltage to the supplied system. There exist strong requirements on the electrical characteristics of regulator circuits. The main task for the voltage regulator is to keep the output voltage (VOUT) regulated at a nominal voltage level. This must be assured in both steady state and transient conditions. If the voltage VOUT goes out of regulation, this can lead to malfunction or even destruction of the supplied system. If the input voltage VIN of the LDO regulator changes over a wide range with a high slew rate, the output voltage VOUT can show different transient response products—for example, overshoots, undershoots. The amplitude of such transient response products depends on the regulator dynamic characteristics. This behavior is usually called the line transient response. It is beneficial to improve the operating characteristic because this will increase the overall regulator capability of keeping the output voltage VOUT constant.
LDO voltage regulators are usually built as feedback regulation systems. The circuit senses an error between the output voltage VOUT and a reference voltage (VREF), and after sufficient multiplication of the error the circuit drives a power pass (transistor) element with an amplified signal. From principle there is always some error between the VOUT and VREF, but because of high gain, the impact on the output voltage VOUT is negligible. Usually the precision of the output voltage VOUT level is impacted much more by an offset of the error amplifier and by the precision of the voltage reference. In steady state, when a supply voltage (VIN) level and the load current (ILOAD) are fixed, the regulator is able to provide a stable output voltage VOUT level. The situation is more problematic when VIN and/or ILOAD are changing, in particular when the change is very fast (for example, due to a transient condition). The LDO regulator as a real electronic circuit has a characteristic response time given by the charge stored inside the system and by the mobility of the charge carriers. For this reason the system is not able to react in an infinitely short time. This is represented as the line/load transient response of the LDO which can be seen on the VOUT waveform as under/over shoots around the nominal VOUT level. The amplitude of the transient response depends on the amplitude of the VIN, the ILOAD stimuli and the slew rate. Small and slow changes may generate relatively small VOUT transients; fast changes with high amplitude may generate relatively large VOUT transients (which may exceed safe limits).
The LDO regulator is known to operate in two conditions depending on the VIN level. If the VIN level is sufficiently in excess of the nominal VOUT voltage, the LDO regulator operates to regulate VOUT at a constant level. If the VIN level drops close to or even below the nominal VOUT voltage, however, the LDO regulator is not able to provide a constant VOUT level and the output voltage drops down. The first condition is referred to in the art as “closed loop” and the second condition is referred to as “open loop.” In the open loop condition, the LDO regulator is not operating as a voltage regulator, per se, but rather behaves like a switch with some characteristic resistance causing some minimum dropout voltage VDROP=VIN−VOUT=ILOAD*RDSON (wherein RDSON is the on-resistance of the drive transistor). The transition between the closed loop condition and the open loop condition is represented by a significant change of operating points inside the LDO circuitry. If the change between the modes is due, for example, to an extreme and very fast VIN change, the circuit will accommodate this change over a short time period and the consequence of this effect is an extreme transient response overshoot and/or undershoot on the output voltage.
The dropout condition itself is not problematic for the LDO regulator, but the transition from the dropout (open loop) to the closed loop condition is. The transition is usually forced by a rising transition of the VIN level. The regulator has to react in a fast way to recover the VOUT regulation. Because there are significant charges stored inside the circuit, it is not possible to recover the regulation in an infinitely short time. The result of this can be a severe overshoot on the regulator output. There is a need in the art to improve significantly this response.
Reference is now made to FIG. 1 showing a conventional voltage regulator circuit 10 of the low drop out (LDO) type. The circuit 10 is of a known configuration including a bandgap voltage reference V1 generator, a LDO OPAMP I1, a power pass (P-channel MOSFET transistor) element M1, a feedback network (RX and R2), and an output storage capacitor COUT. The circuit 10 operates to provide a constant VOUT level, independent of the input voltage VIN level which can usually change over a wide range. The circuit represents a feedback system, driven by an error voltage VERR=VFB−VREF (where VFB is the feedback voltage provided by the resistive divider RX and R2). The error voltage VERR is amplified by the OPAMP M1 and a resulting driving voltage (VGATE) is applied to the gate of the power MOSFET M1. If the error voltage VERR is low, the output voltage VOUT is close to the nominal level and the feedback loop is closed. This condition is achieved when VIN is sufficiently high with respect to the nominal VOUT level and ILOAD. In this condition the operating point of the circuit nodes is set to a normal level and it changes only slightly depending on external conditions (for example, ILOAD, VIN and temperature). However, if the input voltage VIN drops too much such that the LDO regulator is not able to keep the output voltage VOUT constant, the feedback loop goes into the open loop (dropout) condition. Because the error voltage VERR in this case rises too high, the OPAMP generates the voltage VGATE to try to open the power MOSFET as much as possible by overdriving its VGS (gate to source voltage). The VDROP level depends on the RDSON of the power MOSFET and the load current in accordance with the following equation:VDROP=RDSON*ILOAD  (1)
Furthermore, in the dropout condition different nodes of the OPAMP internal structure are pushed into a saturation state. If a fast rising VIN transition subsequently occurs in this condition, forcing the structure from the open loop to the closed loop condition, the circuit structure can have difficulty in discharging the power MOSFET VGS and recovering the normal regulating state of the OPAMP. This is usually accompanied by overshoot on the output voltage VOUT.